Memory is used for storage of data, program code, and/or other information in many electronic products, such as personal computer systems, embedded processor-based systems, video image processing circuits, portable phones, and the like. Memory cells may be provided in the form of a dedicated memory integrated circuit (IC) or may be embedded (included) within a processor or other IC as on-chip memory. Ferroelectric memory, sometimes referred to as “FRAM” or “FERAM”, is a non-volatile form of memory commonly organized in single-transistor, single-capacitor (1T/1C) or two-transistor, two-capacitor (2T/2C) configurations, in which each memory cell includes one or more access transistors. The non-volatility of an FERAM is due to the bi-stable characteristic of the ferroelectric material in the cell capacitor(s). The cells are typically organized in an array, such as folded-bitline, open-bitline architectures, etc., wherein the individual cells are selected by plateline and wordline signals from address decoder circuitry, with the data being read from or written to the cells along bitlines using sense amp circuits.
FIG. 1 illustrates a 1T/1C FERAM cell 10 including a transistor 12 and a ferroelectric cell capacitor 14. A bottom electrode of the cell capacitor 14 is connected to a first source/drain terminal 15 of the transistor 12 and the other capacitor electrode is coupled to a plateline or driveline 20. Data is read from the cell 10 by applying a signal to the gate 16 of the transistor 12 along a corresponding wordline WL, thereby connecting the bottom electrode of the ferroelectric capacitor 14 to the other transistor source/drain at a bitline 18. A pulse signal is applied to the plateline 20, where the potential on the bitline 18 is the capacitor charge divided by the bitline capacitance. The capacitor charge is dependent upon the pre-existing bi-stable polarization state of the ferroelectric material in the capacitor 14, wherein the bitline potential can have two distinct values. A sense amplifier (not shown) is connected to the bitline 18 to detect the voltage associated with a logic value of either 1 or 0. Because such a read operation is destructive, the cell data is then rewritten back to the memory cell 10.
FIG. 2 illustrates a 2T/2C memory cell 30 in a memory array coupled to a complementary pair of bitlines 32 and 34, where the cell 30 comprises cell transistors 36 and 38 and ferroelectric cell capacitors 40 and 42. The first transistor 36 couples the bitline 32 with a first ferroelectric capacitor 40, and the second transistor 38 couples the complementary bitline 34 to a second ferroelectric capacitor 42. The first and second capacitors 40 and 42 have a common plateline 44 to which a signal is applied for polarizing the capacitors 40 and 42 during read and write operations. For a write operation, the transistors 36 and 38 are enabled via a wordline 46 to couple the capacitors 40 and 42 to the complementary logic levels on the bitlines 32 and 34 corresponding to a logic state to be stored in the cell 30. The plateline 44 is pulsed to polarize the capacitors 40, 42 to correspond to the desired logic state. In a read operation, the transistors 36 and 38 are enabled via the wordline 46 to couple the information stored in the ferroelectric capacitors 40 and 42 to the complementary bitline pair 32 and 34, and a pulse is applied to the plateline 44. This provides a differential signal across the bitline pair 32 and 34 that is sensed by a sense amplifier (not shown), wherein the sensed signal has a polarity corresponding to the data read from the cell 30.
Ferroelectric memory cells are often fabricated in stand-alone memory integrated circuits (ICs) and/or in logic circuits having on-board non-volatile memory (e.g., microprocessors, microcontrollers, DSPs, communications chips, etc.). The ferroelectric memory arrays are typically constructed in a device wafer along with CMOS logic circuits, wherein the cell transistors are often formed concurrently with logic transistors in the device, and the ferroelectric capacitors are constructed in a capacitor layer above the wafer substrate. For example, the construction of the ferroelectric cell capacitors may be integrated into a CMOS fabrication process flow after transistor formation (e.g., after ‘front-end’ processing), and before the metalization or interconnection processing (e.g., before ‘back-end’ processing). However, many back-end processing steps include hydrogen, for example, in forming trench etch-stop layers, etch clean operations, copper sintering, and other process steps during metalization. This process hydrogen diffuses into the ferroelectric cell capacitors, causing degradation in the electric properties of the ferroelectric memory cells, including degraded switched polarization. In addition, hydrogen can degrade the performance of transistors in the semiconductor device, for example, causing fixed oxide charge and interface traps at the interface between the transistor gate dielectric and the underlying silicon, leading to negative bias temperature instability (NBTI). This results in reduced drain saturation current (Idsat) and an increase in the transistor threshold voltage (Vsat). Consequently, there is a need for hydrogen barriers and fabrication techniques for protecting ferroelectric capacitors and transistors against hydrogen in back-end and other fabrication processing.